1. Field of the Invention
The present invention generally relates to a method and structure for improving device characteristics and, more particularly, to a method and structure for preventing leakage at an interface (junction) formed between a Source/Drain (S/D) region and a shallow trench isolation (STI) region of a Field Effect Transistor (FET) or other similar device.
2. Background Description
Parasitic leakage paths have been known to occur in contemporary CMOS technologies which employ field effect transistors that are adjacent or bounded by trenches. The trenches may be filled with oxide in order to form isolation structures (shallow trench isolation (STI)) or may provide a location for semiconductor devices, such as, for example, capacitors.
More specifically, it has been found that parasitic leakage results when a divot or recess or both is formed at the interface between the STI oxide region and the Source/Drain (S/D) region (e.g., corner of the SID region adjacent to the STI oxide region). These divots or recesses result from the etching process which forms the STI oxide region.
The divots and recesses form an exposed edge at the corner of the S/D region (adjacent to the STI oxide region) such that a silicide formed on the top of the S/D region will also form on the exposed edge portion of the S/D region. This brings the silicide closer to the junction between the S/D and STI regions (e.g., at the edge of the S/D region adjacent to the STI region), resulting in a leakage path. Moreover, a relatively short path for potential leakage may further result when the S/D junction tilts upward at the interface between the S/D region and the STI region, as may occur from depletion or pile-up of the dopant during oxidation steps.
FIG. 1 illustrates the above situation. Specifically, in FIG. 1, the S/D region has a thickness of xe2x80x9cAxe2x80x9d and the junction depth adjacent to the STI region has a thickness of xe2x80x9cBxe2x80x9d, where xe2x80x9cBxe2x80x9d is less than xe2x80x9cAxe2x80x9d. (It is well known to one of ordinary skill in the art that STI region must be deeper than the S/D region.) In this manner, a recess is formed between the two regions. It is also seen that a divot is formed at the junction between the S/D region and the STI region. Both of these phenomenon result in the corner portion of the S/D region having an exposed corner or edge. This exposed corner or edge, in turn, brings the silicide closer to the junction between the S/D and STI regions causing leakage at this junction.
In other approaches, U.S. Pat. No. 5,837,612 to Ajuria, et al. shows a method for forming STI regions by forming an oxidizable layer made of polysilicon. An opening is patterned and etched through this layer to define and form the STI region. Silicon sidewalls of the trench and the polysilicon layer are then exposed to an oxidizing ambient to form a thermal oxide trench liner and an erosion-protection polysilicon-oxide layer. A trench fill material is then deposited and chemically and mechanically polished (CMP) utilizing the polysilicon layer as a polish stop. The final polished trench fill plug comprises an ozone TEOS bulk material and an annular peripheral upper erosion-protection portion formed of the polysilicon-oxide. However, this reference does not address the placement of a silicide layer which may contribute to the leakage problem, depending on the placement thereof.
U.S. Pat. No. 5,629,544 to Voldman, et al. shows a diode positioned in a well having trench isolation. Both the well contact of the diode and the rectifying contact of the diode are silicided, but the silicide on the rectifying contact is spaced from the trench isolation edge. The spacing is provided by a gate stack or other mask. In one embodiment, the gate stack alone spaces the two diode contacts from each other, eliminating the need for trench isolation. However, by using a gate stack for spacing the diode contacts, parasitic capacitance may increase at the S/D region to the polysilicon layer or shorts or other leakage may result, depending on the specific layout of the Voldman, et al. structure.
The present invention is directed to a method of forming a nitride layer at an interface between a Source/Drain (S/D) region and a shallow trench isolation (STI) region in order to prevent leakage on a device such as, for example, a Field Effect Transistor (FET). The present invention is also directed to the structure of the device.
The present invention includes etching a trench in a semiconductor wafer, and overfilling the trench with oxide. The oxide is then etched back or planarized forming either or both of a recess or a divot at the junction between the planarized oxide (STI region) and an S/D region (to be later formed). A gate oxide is thermally grown over both the substrate and the STI region, and a polysilicon gate is formed over the gate oxide layer, proximate to the STI region. In the preferred embodiment, a space is provided between the polysilicon gate and the STI region so that the S/D region can be properly positioned and formed at a later processing step.
A sidewall oxide layer is formed about the polysilicon gate. The formation of the sidewall oxide will also form a thin layer of oxide over the gate oxide and the STI region, but this thin layer is insignificant and will not affect the device of the present invention. The silicon substrate is then doped at the space between the STI region and the polysilicon gate to form the S/D region.
A blocking nitride layer is formed over the entire surface of the device. This includes forming the nitride layer over the (i) polysilicon gate region, (ii) the S/D region and (iii) the STI region, and most importantly over the interface or junction between the S/D region and the STI region where a divot or recess or both may exist. In one embodiment of the present invention, it is only necessary to form the nitride layer over the interface or junction between the S/D region and the STI region (e.g., over the divot or recess). The nitride layer prevents the formation of a silicide layer to form at the interface between the S/D region and the STI region thus preventing any leakage.
The nitride layer as well as the additional oxide layer is selectively etched, and a uniform layer of cobalt or titanium is then deposited on the device in order to form either cobalt silicide or titanium silicide over the landed or contact area of the S/D region. By using the nitride layer, silicide cannot form over the divots or recesses at the interface between the S/D region and the STI region. Instead, the nitride layer is provided at this interface, which blocks the formation of the silicide. Thus, leakage which would otherwise occur at this interface with prior art systems is prevented.